1. Technical Field
The inventive concept relates to electronic devices. More particularly, the inventive concept relates to on-chip clock controllers and system-on-chips (SOCs).
2. Discussion of the Related Art
An at-speed test may be used to detect a transition delay fault as well as a stuck-at fault in a system-on-chip (SOC) or other electronic devices. The at-speed test may apply a high-speed clock used for normal operation to capture data with a real operating frequency while simultaneously performing a scan operation using a slow scan clock in a scan mode.
For the at-speed test, an on-chip clock controller (OCCC) of a SOC may be employed by a test tool, for example, DFTMAX by Synopsys, Inc., to use the SOC's internal phase locked loop (PLL). The OCCC may be located in each group where circuits using the same clock are grouped into a clock domain.
The OCCC may generate, launch, and capture clocks based on a slow scan clock provided from automatic test equipment (ATE) and a high-speed clock generated by the internal PLL.
Power management may be considered during a manufacturing test. This is so, because as circuit geometry is reduced and threshold voltages become lower, the reliability of a digital integrated circuit (IC) can be adversely affected by excessive power consumption during the test. For example, such factors may result in an initial test failure and a false failure during a final test.